Expect some short downtimes and small glitches during the first week of February.
Unconventional cyclic counter X97508
Design a 3-bit cyclic counter that outputs the sequence 0, 1, 3, 7, 6, 4, 0, 1, … (of period 6).
Specification
module cyclic_counter(count, clk, rst);
output [2:0] count;
input clk, rst;Input
clkis the clock signal.rstis the synchronous reset signal.
Output
countis the output of the counter.
Information
- Author
- Jordi Cortadella
- Language
- English
- Official solutions
- Verilog
- User solutions
- Verilog