Design a sequential circuit described by the following state diagram.
The circuit has two inputs () and one output (). The inputs can take the values 00, 01 and 10 (the value 11 will never occur and can be considered as a don’t care).
module state_machine(x, z, clk, rst);
input [1:0] x;
input clk, rst;
output z;clk is the clock signal.
rst is the synchronous reset signal.
x are the two input signals.
z is the ouput signal.