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4-bit counter X35277
Design a circuit that implements a 4-bit counter (mod 16). The counter must start at zero after reset and increase the value at each cycle.
Specification
module counter4(count, clk, rst);
input clk, rst;
output [3:0] count;Input
clkis the clock signal.rstis the synchronous reset signal.
Output
countis the 4-bit output of the counter.
Information
- Author
- Jordi Cortadella
- Language
- English
- Official solutions
- Verilog
- User solutions
- Verilog