Design a sequential circuit that generates the Fibonacci series. The
circuit will represent the numbers with
bits and will generate the Fibonacci numbers
.
At each cycle, a new number must be generated. The following waveform
illustrates the behavior of the circuit.
The circuit must be designed to represent the numbers with 6 bits.
module fibonacci(clk, rst, fib);
input clk, rst;
output [5:0] fib;clk is the clock signal.
rst is the synchronous reset signal.
fib is the Fibonacci number generated at each
cycle.