2-input multiplexer (4-bit wide) X82780


Statement
 

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Design a 2-input multiplexer in which the inputs are 4-bit wide. The selection signal is called sel, whereas the two inputs are called in0 and in1. The output will be in0 when sel=0 and in1 when sel=1.

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Specification

module mux4(in0, in1, sel, out);
    input [3:0] in0, in1;
    input sel;
    output [3:0] out;

Input

  • in0 and in1 are the two 4-bit inputs.

  • sel is the selector.

Output

  • out is the 4-bit output.

Information
Author
Javier de San Pedro Martín and Marta Miralpeix Anglerill
Language
English
Official solutions
Verilog
User solutions
Verilog