Design a sequential circuit with one binary input and one binary
output. The output at time
is 1 when the input in the time interval
is 0101 or 0110.
module sequence(in, out, clk, rst);
input in, clk, rst;
output out;The state machine can be implemented with 5 states.
in is the input of the state machine.
clk is the clock signal.
rst is the synchronous reset signal.
out is the output of the state machine.