Expect some short downtimes and small glitches during the first week of February.
Even number X36253
Design a circuit that receives a 4-bit number as input and produces an output that is asserted when the input number is even.
Specification
module even4(number, even);
input [3:0] number;
output even;Input
numberis the 4-bit input number.
Output
evenindicates when the input number is even.
Information
- Author
- Jordi Cortadella
- Language
- English
- Official solutions
- Verilog
- User solutions
- Verilog