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2-input multiplexer X12031

Statement

Design a 2-input multiplexer with basic gates. The selection signal is called sel, whereas the two inputs are called in0 and in1. The output will be in0 when sel=0 and in1 when sel=1.

Specification

module mux(in0, in1, sel, out);
    input in0, in1, sel;
    output out;

Input

in0 and in1 are the signals to be selected.
sel is the selection signal.

Output

out is the output of the multiplexer.

Information

Author: Jordi Cortadella
Language: English
Official solutions: Verilog
User solutions: Verilog