Sequential adder X09271


Statement
 

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Design a circuit that calculates the addition of two numbers sequentially. The circuit has two inputs, a and b that provide one binary digit at each cycle (starting from the least-significant bits). At each cycle, the circuit produces a binary digit of the addition.

Here is an example of a sequence of cycles (note that time moves from right to left):

  cycle:    ... 7 6 5 4 3 2 1 0
  -----------------------------
  a:        ... 1 0 0 1 1 0 1 0
  b:        ... 0 0 0 1 0 1 1 1
  -----------------------------
  sum:      ... 1 0 1 1 0 0 0 1

Specification

module sequential_adder (a, b, sum, clk, rst); input a, b, clk, rst; output sum;

Input

  • a and b are the two sequential inputs.
  • clk is the clock signal.
  • rst is the reset signal.

Output

  • sum generates the addition of aand b sequentially.
Information
Author
Jordi Cortadella
Language
English
Official solutions
Unknown. This problem is being checked.
User solutions
Verilog