Bus transfer or invert X00341


Statement
 

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Design a circuit that transfers or inverts the value of an NN-bit bus. A control signal called invert will determine whether the value must be transferred (invert=0) or inverted (invert=1). NN must be a parameter of the circuit with default value 8.

Specification

module bus_transfer_invert(in, invert, out);
    parameter N=8;
    input [N-1:0] in;
    input invert;
    output [N-1:0] out;

Input

  • in is the NN-bit input bus.

  • invert is the control signal that determines whether the value of the bus must be transferred or inverted.

Output

  • out is the NN-bit inverted value of the bus.

Information
Author
Jordi Cortadella
Language
English
Official solutions
Verilog
User solutions
Verilog