Unconventional cyclic counter

Design a 3-bit cyclic counter that outputs the sequence 0, 1, 3, 7, 6, 4, 0, 1, … (of period 6).

Specification

module cyclic_counter(count, clk, rst);
    output [2:0] count;
    input clk, rst;

Input

• clk is the clock signal.

• rst is the synchronous reset signal.

Output

• count is the output of the counter.

Problem information

Author: Jordi Cortadella

Generation: 2026-02-03T12:20:52.543Z

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