Mod-7 up-down counter

Design a mod-7 up-down counter. The counter must count-up when the input
signal up is 1. Otherwise, the counter must count-down. After reset, the
counter must be initialized at zero.

Specification

    module updown_mod7(up, count, clk, rst);
        input up, clk, rst;
        output [2:0] count;

Input

- up is the input signal that indicates when the counter must
  count-up (1) or count-down (0).

- clk is the clock signal.

- rst is the synchronous reset signal.

Output

- count is the 3-bit output.

Problem information

Author: Jordi Cortadella

Generation: 2026-02-03T12:24:34.568Z

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