4-bit counter

Design a circuit that implements a 4-bit counter (mod 16). The counter
must start at zero after reset and increase the value at each cycle.

Specification

    module counter4(count, clk, rst);
        input clk, rst;
        output [3:0] count;

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Input

- clk is the clock signal.

- rst is the synchronous reset signal.

Output

- count is the 4-bit output of the counter.

Problem information

Author: Jordi Cortadella

Generation: 2026-06-09T11:00:35.433Z

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